US 12,353,811 B2
Out-of-context timing constraints modification for interior pins
Saurabh Gupta, Bangalore (IN); Chithra Ravindranath, Horamavu (IN); and Gireesh Kumar K M, Bangalore (IN)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Feb. 18, 2022, as Appl. No. 17/674,890.
Prior Publication US 2023/0267251 A1, Aug. 24, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
moving at least one pin of a macro during synthesis for an integrated circuit (IC), the macro being part of a unit, the moving being in response to performing the synthesis on a specification for the IC;
determining a distance that the at least one pin moved from an original location to a new location in the macro;
checking whether parent layer information of the unit is available for interior pins to determine the delay of a metal layer associated with the distance, wherein a determination is made to use one of a first option or a second option for a metal level of the metal layer, wherein the first option comprises using the metal level according to that which is utilized in the unit when the parent layer information of the unit is available, wherein the second option comprises determining that the metal level is to be one level higher than that which is utilized in the macro;
determining a delay based at least in part on the distance that is moved and the metal level of the metal layer for one of the first option and the second option; and
using the delay to determine a signal timing at the least one pin at the new location in the macro.