US 12,353,810 B2
Unified power format annotated RTL image recognition to accelerate low power verification convergence
Zamrath Nizam, Colombo (LK); Chirath Chamikara Diyagama, Colombo (LK); Bhaskar Pal, Cupertino, CA (US); and Ashan Wickramasinghe, Colombo (LK)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jul. 19, 2022, as Appl. No. 17/868,325.
Claims priority of application No. 202141032565 (IN), filed on Jul. 20, 2021.
Prior Publication US 2023/0043751 A1, Feb. 9, 2023
Int. Cl. G06F 30/33 (2020.01); G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings;
generating an RTL feature array from the RTL code;
arranging features based on a UPF into a UPF feature array;
generating, by a processor, a combined feature array for the particular IC design based on the RTL feature array and the UPF feature array;
comparing the combined feature array for the particular IC design with another combined feature array; and
reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.