US 12,353,770 B2
Adaptive block mapping
Alberto Sassara, Naples (IT); Giuseppe D'Eliseo, Caserta (IT); Lalla Fatima Drissi, Ottaviano (IT); Luigi Esposito, Piano di Sorrento (IT); Paolo Papa, Naples (IT); Salvatore Del Prete, Grumo Nevano (IT); Xiangang Luo, Fremont, CA (US); and Xiaolai Zhu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 23, 2024, as Appl. No. 18/586,207.
Application 18/586,207 is a continuation of application No. 17/750,131, filed on May 20, 2022, granted, now 11,922,069.
Prior Publication US 2024/0272832 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more memories comprising a plurality of planes that each comprise a plurality of blocks; and
one or more controllers coupled with the one or more memories and operable to:
write, in a first mode, a first portion of first data to a first set of blocks of the plurality of blocks and a second portion of the first data to a first subset of a second set of blocks of the plurality of blocks based at least in part on receiving one or more commands from a host device, wherein the first mode comprises writing a plurality of bits of data per memory cell; and
write, in a second mode, a third portion of the first data to a second subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device, wherein the second mode comprises writing one bit of data per memory cell.