| CPC G06F 3/0659 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0673 (2013.01)] | 21 Claims |
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1. A circuit, comprising:
a memory array having a plurality of memory devices, each of the memory devices including:
a memory configured to store packet data, and
a request arbiter configured to interface with at least one other memory device of the memory array, the request arbiter configured to:
filter invalid requests from a plurality of requestors;
determine a bitvector representing a sequence of the plurality of requestors, the bitvector indicating whether each of the plurality of requestors has a valid request,
output a first parallel signal representing the bitvector,
shift the first parallel signal relative to the bitvector in response to a shift signal,
output a second parallel signal indicating a bit of the parallel signal corresponding to a first request to be serviced by the memory device, and
shift the bitvector to determine a second request to be serviced by the memory device; and
a memory interface configured to route requests from a requestor to the memory array.
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