US 12,353,756 B1
Systems and methods for joint de-interleaving and rate recovery in a receiver
Thirunathan Sutharsan, San Diego, CA (US); Mohanned Sinnokrot, San Diego, CA (US); Wai Chan, San Diego, CA (US); and Mihail Petrov, San Diego, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 19, 2022, as Appl. No. 17/664,205.
Claims priority of provisional application 63/261,649, filed on Sep. 24, 2021.
Int. Cl. G06F 3/06 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01); G06F 12/0802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a combiner unit configured to receive a plurality of new data elements for a subset of positions in a code block and a plurality of existing data elements for the subset of positions in the code block and configured to compute a plurality of updated data elements for the subset of positions in the code block;
a cache coupled to the combiner unit and configured to receive and store the plurality of updated data elements;
a code block buffer coupled to the combiner unit and configured to store a set of data elements for the code block at a plurality of locations such that different locations in the plurality of locations correspond to different positions in the code block, the code block buffer being further configured to receive and store the plurality of updated data elements in the locations corresponding to the subset of positions in the code block;
a selection circuit configured to receive a plurality of first input data elements from the cache and configured to receive a plurality of second input data elements from the code block buffer and to selectably provide either the first input data elements or the second input data elements as the existing data elements to the combiner unit; and
a controller unit coupled to the combiner unit, the cache, and the code block buffer, wherein the controller unit is configured to:
determine, based on a rate-matching pattern associated with the code block, a target location in the code block buffer for the plurality of new data elements;
detect an address collision condition with respect to the target location; and
control the cache, the code block buffer, and the selection circuit such that when the address collision condition is detected, the cache provides a cached plurality of updated data elements associated with the target location to the selection circuit and the selection circuit provides the first input data elements as the existing data elements to the combiner unit.