US 12,353,755 B2
Host verification for a memory device
Aaron P. Boehm, Boise, ID (US); Steffen Buch, Munich (DE); and Lance W. Dover, Fair Oaks, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 9, 2024, as Appl. No. 18/660,070.
Application 18/660,070 is a continuation of application No. 17/396,529, filed on Aug. 6, 2021, granted, now 12,001,707.
Claims priority of provisional application 63/068,044, filed on Aug. 20, 2020.
Prior Publication US 2024/0361950 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive, at a memory device of the one or more memory devices, a first value that is associated with an identification of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
receive an access command;
suspend executing the access command based at least in part on the memory device operating in the first functionality mode;
transmit a second value that is based at least in part on the first value and comprises a random set of bits;
receive data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device;
enable the second functionality mode of the second power mode of the memory device based at least in part on the encrypted third value; and
cease suspension of the access command based at least in part on enabling the second functionality mode.