US 12,353,753 B2
Diagonal page mapping in memory systems
Tawalin Opastrakoon, Boise, ID (US); Renato C. Padilla, Folsom, CA (US); Michael G. Miller, Boise, ID (US); Christopher M. Smitchger, Boise, ID (US); Gary F. Besinga, Boise, ID (US); Sampath K Ratnam, San Jose, CA (US); and Vamsi Pavan Rayaprolu, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Oct. 31, 2022, as Appl. No. 17/978,050.
Application 17/978,050 is a continuation of application No. 17/339,660, filed on Jun. 4, 2021, granted, now 11,507,304.
Prior Publication US 2023/0049877 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 3/0689 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a first host data item;
storing the first host data item in a first page of a first logical unit of the memory device, wherein the first page is one of a plurality of pages associated with redundancy metadata;
receiving a second host data item, wherein the second host data item consecutively follows the first host data item according to an order in which the first host data item and the second host data item are received;
identifying a second page of a second logical unit of the memory device, wherein the second page is one of the plurality of pages associated with the redundancy metadata, and wherein the first page and the second page are associated with different wordlines of the memory device; and
storing the second host data item in the second page of the second logical unit of the memory device.