US 12,353,738 B2
Techniques for memory system standby mode control
Junam Kim, Seoul (KR)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 16, 2024, as Appl. No. 18/444,064.
Claims priority of provisional application 63/446,696, filed on Feb. 17, 2023.
Prior Publication US 2024/0281158 A1, Aug. 22, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
one or more memory devices of a memory system; and
a controller of the memory system coupled with the one or more memory devices and configured to cause the apparatus to:
receive an indication to enter a standby mode;
transmit, based on receiving the indication to enter the standby mode, an indication of a duration associated with delayed entry into the standby mode;
perform background operations at the memory system based on transmitting the indication of the duration associated with the delayed entry into the standby mode; and
enter the standby mode after performing the background operations.