US 12,353,729 B2
Triple activate command row address latching
Kwang-Ho Cho, Boise, ID (US); Miki Matsumoto, Boise, ID (US); and Kevin J. Ryan, Elizabeth, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,222.
Prior Publication US 2024/0069759 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first activate command that indicates a first set of row address bits indicative of a first portion of a row address;
receiving, after receiving the first activate command, a second activate command that indicates a second set of row address bits indicative of a second portion of the row address;
receiving, after receiving the second activate command, a third activate command that indicates a third set of row address bits indicative of a third portion of the row address; and
activating a row of memory cells based at least in part on receiving the first activate command, the second activate command, and the third activate command, wherein the row of memory cells is addressed according to the first set of row address bits, the second set of row address bits, and the third set of row address bits.