US 12,353,723 B2
Low-power boot-up for memory systems
Reshmi Basu, Boise, ID (US); Jonathan S. Parry, Boise, ID (US); David Aaron Palmer, Boise, ID (US); Luca Porzio, Casalnuovo (IT); Giuseppe Cariello, Boise, ID (US); and Stephen Hanna, Fort Collins, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,294.
Prior Publication US 2024/0045596 A1, Feb. 8, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0617 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a first communication interface comprising a plurality of conductive paths;
a second communication interface comprising a first conductive path and a second conductive path; and
a controller associated with the memory system, wherein the controller is configured to cause the memory system to:
receive, over the first conductive path, a first indication to boot-up the memory system and the first communication interface associated with the memory system;
receive, over the second conductive path, a second indication of whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication, wherein a value of the second indication is based least in part on whether a charge state of a power supply is sufficient to activate the memory system and the first communication interface in the high-power mode, and wherein receiving the second indication over the second conductive path of the second communication interface instead of the first communication interface prevents the memory system from entering a power reset loop when the charge state of the power supply is insufficient to activate the first communication interface in the high-power mode; and
boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.