US 12,353,722 B2
Information processing apparatus, method for controlling information processing apparatus, non-transitory recording medium storing control tool, host device, non-transitory recording medium storing performance evaluation tool, and performance evaluation method for external memory device
Daisuke Hashimoto, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jun. 16, 2023, as Appl. No. 18/336,188.
Application 18/336,188 is a continuation of application No. 17/445,273, filed on Aug. 17, 2021, granted, now 11,726,661.
Application 17/445,273 is a continuation of application No. 16/567,693, filed on Sep. 11, 2019, granted, now 11,119,661, issued on Sep. 14, 2021.
Application 16/567,693 is a continuation of application No. 16/123,586, filed on Sep. 6, 2018, granted, now 10,452,283, issued on Oct. 22, 2019.
Application 16/123,586 is a continuation of application No. 15/399,475, filed on Jan. 5, 2017, granted, now 10,101,923, issued on Oct. 16, 2018.
Application 15/399,475 is a continuation of application No. 14/178,654, filed on Feb. 12, 2014, granted, now 9,594,611, issued on Mar. 14, 2017.
Application 14/178,654 is a continuation of application No. PCT/JP2012/070777, filed on Aug. 9, 2012.
Claims priority of application No. 2011-179890 (JP), filed on Aug. 19, 2011; and application No. 2011-186542 (JP), filed on Aug. 29, 2011.
Prior Publication US 2023/0342039 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/177 (2006.01); G06F 3/06 (2006.01); G06F 9/4401 (2018.01); G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01); G06F 11/34 (2006.01); G06F 12/10 (2016.01); G11C 29/52 (2006.01); G06F 9/445 (2018.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0652 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 9/4401 (2013.01); G06F 11/004 (2013.01); G06F 11/0754 (2013.01); G06F 11/1068 (2013.01); G06F 11/1417 (2013.01); G06F 11/1456 (2013.01); G06F 11/3485 (2013.01); G06F 12/10 (2013.01); G11C 29/52 (2013.01); G06F 9/4403 (2013.01); G06F 9/4406 (2013.01); G06F 9/4416 (2013.01); G06F 9/44505 (2013.01); G06F 11/1461 (2013.01); G06F 11/3419 (2013.01); G06F 2201/81 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/65 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A host device to which a semiconductor memory device is connectable,
the semiconductor memory device comprising:
a nonvolatile semiconductor memory including memory cells for storing data, and configured to electrically erase, in a first unit, data stored in the memory cells, the first unit including the plurality of memory cells;
a volatile semiconductor memory;
a controller; and
a host interface,
each of the nonvolatile semiconductor memory and the volatile semiconductor memory being configured to store first information for specifying a physical address of the nonvolatile semiconductor memory corresponding to logical address information received via the host interface,
when receiving a write command via the host interface, the controller being configured to generate a correction code by using data specified by the received write command and to store the data and the correction code in the nonvolatile semiconductor memory, and
when receiving a read command via the host interface, based on data and a corresponding correction code read from the nonvolatile semiconductor memory using the first information, the controller being configured to correct the read data,
the nonvolatile semiconductor memory being configured to further store:
second information based on a total number of pieces of write data received according to the received write command;
third information based on a total number of pieces of data read from the nonvolatile semiconductor memory according to the received read command;
fourth information related to a number of pieces of data that have not been corrected by using the corresponding correction code among data read from the nonvolatile semiconductor memory;
fifth information indicating, with the first unit, information corresponding to a number of memory cells in the nonvolatile semiconductor memory that are determined to be unable to write data therein; and
sixth information corresponding to a number of the memory cells in the nonvolatile semiconductor memory that are determined to be able to write data therein, wherein
the host device is configured to:
transmit the write command and the read command to the semiconductor memory device;
read the second information from the semiconductor memory device;
read the third information from the semiconductor memory device;
read the fourth information from the semiconductor memory device;
read the fifth information from the semiconductor memory device;
read the sixth information from the semiconductor memory device;
display, on a display device connected to the host device, first status information of the nonvolatile semiconductor memory based on the read second information or the read third information, and second status information of the nonvolatile semiconductor memory based on the read fourth information or the read fifth information, the second status information indicating a remaining lifespan of the semiconductor memory device; and
display, when the remaining lifespan becomes less than a first threshold, a warning screen on the display device, the warning screen including a message that prompts back up of data stored in the semiconductor memory device.