US 12,353,717 B2
Localized and relocatable software placement and NoC-based access to memory controllers
Aman Gupta, Sunnyvale, CA (US); Krishnan Srinivasan, San Jose, CA (US); Shishir Kumar, Hyderabad (IN); Sagheer Ahmad, Cupertino, CA (US); and Ahmad R. Ansari, San Jose, CA (US)
Assigned to Xilnix, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Dec. 22, 2022, as Appl. No. 18/145,339.
Prior Publication US 2024/0211138 A1, Jun. 27, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of processing elements;
a plurality of memory controllers; and
a network on chip (NoC) providing connectivity between the plurality of processing elements and the plurality of memory controllers, the NoC including:
a sparse network coupled to the plurality of processing elements, wherein the sparse network includes a plurality of interconnected switches having routing tables; and
a non-blocking network coupled to the sparse network and the plurality of memory controllers, wherein the non-blocking network includes a plurality of crossbars, each crossbar couples the sparse network to a subset of the plurality of memory controllers, and each subset includes at least a first memory controller and a second memory controller;
wherein the sparse network implements a first portion of a path coupling one or more selected processing elements of the plurality of processing elements to the non-blocking network, the non-blocking network implements a second portion of the path, and a crossbar of the second portion of the path connects the one or more selected processing elements to the first memory controller or the second memory controller while maintaining a same delay for memory access performance.