US 12,353,715 B2
Near-memory engine for reducing bandwidth utilization in sparse data applications
Sriseshan Srikanth, Austin, TX (US); and Vignesh Adhinarayanan, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 30, 2021, as Appl. No. 17/490,909.
Prior Publication US 2023/0102690 A1, Mar. 30, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device, comprising
address generation circuitry configured to receive a command from a processing device;
a memory interface coupled with the address generation circuitry and configured to read original data from a set of one or more memory devices based on an address range specified in the command; and
zero detection circuitry coupled with the memory interface and configured to, in response to the command, select a subset of the original data for transmitting to the processing device, wherein the subset includes fewer zero values than the original data.