US 12,353,713 B2
Memory controller with common request buffer
Lunkai Zhang, Portland, OR (US); Rasmus Madsen, Copenhagen (DK); and Martin Lueker-Boden, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 27, 2023, as Appl. No. 18/360,535.
Claims priority of provisional application 63/489,615, filed on Mar. 10, 2023.
Prior Publication US 2024/0302964 A1, Sep. 12, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A control circuit configured to communicate with a non-volatile memory array that stores data at a plurality of addresses, the control circuit comprising:
an interface configured to receive requests;
a common request queue connected to the interface, the common request queue configured to receive the requests from the interface in a received order, store the requests and output the requests for a first address in the received order for the first address; and
a common request buffer connected to the common request queue, the common request buffer configured to receive the requests for the first address from the common request queue in the received order, buffer unfinished requests directed to the plurality of addresses in corresponding entries such that for each unfinished request a corresponding entry in the common request buffer includes an address to which the unfinished request is directed and a request type from a plurality of types including at least read and write, the common request buffer configured to block receipt of requests from the common request queue according to addresses in entries in the common request buffer such that for any specified address in the non-volatile memory array no more than one unfinished request is in the common request buffer and additional requests to the specified address are blocked so that they remain in the common request queue.