US 12,353,505 B2
Methods and apparatus for performing diversity matrix operations within a memory array
Fa-Long Luo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 6, 2023, as Appl. No. 18/502,435.
Application 18/502,435 is a division of application No. 16/705,096, filed on Dec. 5, 2019, granted, now 11,853,385.
Prior Publication US 2024/0078286 A1, Mar. 7, 2024
Int. Cl. G06F 17/16 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01); G11C 13/00 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 12/0207 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G06F 2212/454 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a processor apparatus coupled to a non-transitory computer readable medium storing one or more instructions which, when executed by the processor apparatus, cause the device to:
write a processing matrix operation opcode to the non-transitory computer readable medium, wherein:
the processing matrix operation opcode causes the non-transitory computer readable medium to operate at least one array of memory cells as a matrix structure; and
modifies one or more analog values of the matrix structure; and
read a matrix transformation result from the matrix structure.