US 12,353,503 B2
Output array neuron conversion and calibration for analog neural memory in deep learning artificial neural network
Hieu Van Tran, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Vipin Tiwari, Dublin, CA (US); Mark Reiten, Alamo, CA (US); and Nhan Do, Saratoga, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Jun. 21, 2019, as Appl. No. 16/449,205.
Claims priority of provisional application 62/842,279, filed on May 2, 2019.
Prior Publication US 2020/0349422 A1, Nov. 5, 2020
Int. Cl. G11C 16/08 (2006.01); G06F 17/16 (2006.01); G06N 3/065 (2023.01); G11C 11/54 (2006.01); G11C 16/04 (2006.01)
CPC G06F 17/16 (2013.01) [G06N 3/065 (2023.01); G11C 11/54 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 2216/04 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method, comprising:
measuring leakage current from one or more decoding circuits and one or more column write circuits for use with a non-volatile memory array and storing a measured leakage current value in a register;
retrieving the leakage current value from the register; and
converting a neuron output from the non-volatile memory array into a digital value and subtracting the leakage current value from the digital value.