US 12,353,345 B2
Multi-path universal asynchronous transceiver and transmission method thereof
GuoFeng Zhang, Suzhou (CN); YingXue Wang, Suzhou (CN); Hui Shen, Suzhou (CN); and ZhaoMing Li, Suzhou (CN)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Jun. 21, 2023, as Appl. No. 18/338,466.
Claims priority of application No. 202211101254.3 (CN), filed on Sep. 9, 2022.
Prior Publication US 2024/0086351 A1, Mar. 14, 2024
Int. Cl. G06F 13/366 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/366 (2013.01) [G06F 13/1673 (2013.01); G05B 2219/33182 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A multi-path universal asynchronous transceiver, comprising:
a first buffer caching at least one of first log information;
a second buffer caching at least one of second log information; and
a tx aggregation and arbitration circuit respectively coupled to the first buffer and the second buffer, and having a predetermined threshold;
wherein the tx aggregation and arbitration circuit: polls the first buffer and the second buffer according to the predetermined threshold; performs an arbitration procedure between the first buffer and the second buffer to obtain at least one of first log information packet and at least one of second log information packet correspondingly,
wherein the at least one of first log information packet and the at least one of second log information packet respectively comprise a header; the header comprises a synchronous pattern data, a path number data, and a checksum data.