US 12,353,341 B2
Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection
Bhupender Singh, New Delhi (IN); Hitesh Chawla, Noida (IN); Tanuj Kumar, Noida (IN); Harsh Rawat, Faridabad (IN); Kedar Janardan Dhori, Ghaziabad (IN); Promod Kumar, Greater Noida (IN); Manuj Ayodhyawasi, Noida (IN); and Nitin Chawla, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Oct. 12, 2023, as Appl. No. 18/379,373.
Claims priority of provisional application 63/419,457, filed on Oct. 26, 2022.
Prior Publication US 2024/0143239 A1, May 2, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory circuit, comprising:
a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to memory cells of the column;
a row decoder circuit operating in response to an internal clock and a received address to selectively actuate one of the word lines with a word line signal through a word line driver and further actuate a dummy word line with a dummy word line signal through a dummy word line driver; and
a control circuit comprising:
a clock generator configured to generate said internal clock, wherein said internal clock is reset in response to a reset signal;
a first delay circuit receiving the dummy word line signal from the dummy word line and outputting a first delayed dummy word line signal;
a second delay circuit receiving the dummy word line signal from the dummy word line and outputting a second delayed dummy word line signal; and
a first multiplexer circuit configured to receive the first and second delayed dummy word line signals and select said first delayed dummy word line signal for output as said reset signal in response to a first logic state of a mode control signal and select said second delayed dummy word line signal for output as said reset signal in response to a second logic state of the mode control signal.