US 12,353,337 B2
Methods and circuits for aggregating processing units and dynamically allocating memory
Steven C. Woo, Saratoga, CA (US); and Thomas Vogelsang, Mountain View, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 18/025,571
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Aug. 30, 2021, PCT No. PCT/US2021/048193
§ 371(c)(1), (2) Date Mar. 9, 2023,
PCT Pub. No. WO2022/060559, PCT Pub. Date Mar. 24, 2022.
Claims priority of provisional application 63/080,607, filed on Sep. 18, 2020.
Prior Publication US 2023/0342310 A1, Oct. 26, 2023
Int. Cl. G06F 13/16 (2006.01); G06N 3/048 (2023.01); G06N 3/084 (2023.01)
CPC G06F 13/1668 (2013.01) [G06N 3/048 (2023.01); G06N 3/084 (2013.01); G06F 2213/16 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
stacked memory dies each having memory banks, the stacked memory dies including a first memory bank and a second memory bank; and
a processor die bonded to the stacked memory dies and having:
a first processing unit;
a second processing unit;
a first inter-die memory channel proximate to the first processing unit, remote from the second processing unit, and communicatively coupled to the first memory bank;
a second inter-die memory channel proximate to the second processing unit, remote from the first processing unit, and communicatively coupled to the second memory bank; and
a switch matrix communicatively coupled to the first processing unit, the first inter-die memory channel, the second processing unit, and the second inter-die memory channel, the switch matrix to selectively couple either of the first processing unit and the second processing unit to either of the first inter-die memory channel and the second inter-die memory channel;
each of the first processing unit and the second processing unit including:
an input port communicatively coupled to the switch matrix to receive read data from the communicatively coupled one of the first memory bank and the second memory bank; and
an output port communicatively coupled to the switch matrix to convey write data to the communicatively coupled one of the first memory bank and the second memory bank;
the switch matrix comprising a first switch communicatively coupled between the output port of the first processing unit and the input port of the second processing unit.