US 12,353,330 B2
Preemption techniques for memory-backed registers
Benjiman L. Goodman, Austin, TX (US); Yoong Chert Foo, London (GB); Karl D. Mann, Orlando, FL (US); Terence M. Potter, Austin, TX (US); Frank W. Liljeros, Sanford, FL (US); and Jeffrey T. Brady, Orlando, FL (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 10, 2022, as Appl. No. 18/054,388.
Claims priority of provisional application 63/376,176, filed on Sep. 19, 2022.
Prior Publication US 2024/0095176 A1, Mar. 21, 2024
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0811 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0811 (2013.01); G06F 2212/6042 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
operating, by a computing device, on operands in architectural registers to execute instructions of threads, wherein data for the architectural registers is stored and backed by a memory hierarchy that includes one or more cache levels and one or more memory circuits;
in response to a context switch indication for a given thread, the computing device:
identifying a set of cache lines at a first cache level that stored, prior to the context switch indication, a set of architectural register data for the given thread;
flushing and invalidating the identified set of cache lines; and
storing memory page information that indicates backing memory pages of the set of cache lines that were flushed and invalidated.