US 12,353,307 B2
Random instruction-side stressing in post-silicon validation
Hillel Mendelson, Melbourne (AU); and Tom Kolan, Haifa (IL)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Apr. 18, 2022, as Appl. No. 17/722,430.
Prior Publication US 2023/0333950 A1, Oct. 19, 2023
Int. Cl. G06F 11/27 (2006.01); H01L 21/66 (2006.01)
CPC G06F 11/27 (2013.01) [H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
at least one hardware processor; and
a non-transitory computer-readable storage medium having stored thereon program instructions, the program instructions executable by the at least one hardware processor to:
provide a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads,
generate and store, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template,
build, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads, and
executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads.