US 12,353,305 B2
Compliance and debug testing of a die-to-die interconnect
Swadesh Choudhary, Mountain View, CA (US); Narasimha Lanka, Dublin, CA (US); Debendra Das Sharma, Saratoga, CA (US); Lakshmipriya Seshan, Sunnyvale, CA (US); Zuoguo Wu, San Jose, CA (US); and Gerald Pasdast, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 20, 2022, as Appl. No. 17/844,348.
Claims priority of provisional application 63/295,110, filed on Dec. 30, 2021.
Prior Publication US 2022/0318111 A1, Oct. 6, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/263 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/263 (2013.01) [G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die comprising:
a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect having a mainband and a sideband, wherein the physical layer circuitry is to
reverse a logical lane order of at least some of a plurality of data lanes of the mainband when a lane reversal with respect to the first die and the second die is detected,
wherein during a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers.