US 12,353,280 B2
Erroneous bit discovery in memory system
Joseph Thomas Pawlowski, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Dec. 14, 2023, as Appl. No. 18/540,351.
Application 18/540,351 is a continuation of application No. 17/690,682, filed on Mar. 9, 2022, granted, now 11,853,158.
Application 17/690,682 is a continuation of application No. 16/863,966, filed on Apr. 30, 2020, granted, now 11,288,118, issued on Mar. 29, 2022.
Application 16/863,966 is a continuation of application No. 16/516,897, filed on Jul. 19, 2019, granted, now 10,949,293, issued on Mar. 16, 2021.
Claims priority of provisional application 62/702,766, filed on Jul. 24, 2018.
Prior Publication US 2024/0160522 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G11C 11/409 (2006.01)
CPC G06F 11/102 (2013.01) [G06F 11/1056 (2013.01); G11C 11/409 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
monitoring, by a power management component, a power level associated with a memory system;
determining that the power level varies from a first power level associated with the memory system based at least in part on monitoring the power level, wherein one or more background operations are interrupted in response to the power level varying from the first power level, and wherein the one or more background operations comprise operations independent of an access command from a host;
transmitting a signal indicating that the power level varies from the first power level based at least in part on the determination; and
resuming the one or more background operations based at least in part on information associated with the signal being restored.