US 12,353,271 B2
Error rate interrupts in hardware for high-speed signaling interconnect
Adithya Hrudhayan Krishnamurthy, Sunnyvale, CA (US); and Ish Chadha, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Dec. 1, 2023, as Appl. No. 18/526,621.
Application 18/526,621 is a continuation of application No. 17/557,836, filed on Dec. 21, 2021, granted, now 11,880,265.
Prior Publication US 2024/0103951 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/07 (2006.01); G06F 11/16 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 11/0745 (2013.01); G06F 11/0757 (2013.01); G06F 11/0772 (2013.01); G06F 11/1679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver device comprising:
detection logic to detect frame errors in data frames received by a transmitter device;
error counter logic coupled to the detection logic, wherein the error counter logic is to:
increment a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic;
reduce the first value to a second value for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period, wherein the second value is a non-zero value; and
reset the first value or the second value of the error count to zero responsive to receiving a reset signal; and
threshold logic coupled to the error counter logic, the threshold logic to compare a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.