US 12,353,266 B2
Adaptive frequency control in integrated circuits
Derek James Basehore, Mountain View, CA (US); and Nick Sanders, Saratoga, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Appl. No. 18/006,828
Filed by Google LLC, Mountain View, CA (US)
PCT Filed Jul. 27, 2020, PCT No. PCT/US2020/043749
§ 371(c)(1), (2) Date Jan. 25, 2023,
PCT Pub. No. WO2022/025861, PCT Pub. Date Feb. 3, 2022.
Prior Publication US 2023/0280816 A1, Sep. 7, 2023
Int. Cl. G06F 1/324 (2019.01); H03K 5/135 (2006.01)
CPC G06F 1/324 (2013.01) [H03K 5/135 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for adaptively controlling a frequency of an output clock signal, the output clock signal controlling timing of an integrated circuit, the method comprising:
receiving an input clock signal comprising a first set of multiple clock cycles;
determining, based on an output of a sensor operably coupled to the integrated circuit, a reduction amount by which to reduce the frequency of the output clock signal;
selectively gating, for the first set of multiple clock cycles of the input clock signal, one clock cycle of the first set of multiple clock cycles of the input clock signal to generate a gated clock signal comprising a second set of multiple clock cycles, the second set of multiple clock cycles of the gated clock signal having one fewer clock cycle than the first set of multiple clock cycles of the input clock signal over a same duration of time;
delaying rising transitions and falling transitions of the second set of multiple clock cycles of the gated clock signal to generate the output clock signal comprising a third set of multiple clock cycles, the delaying causing the frequency of the output clock signal to be lower than a frequency of the input clock signal by the reduction amount, the delaying of the rising transitions and the falling transitions of the second set of multiple clock cycles comprising:
applying a first delay offset to a rising transition and a falling transition of a first clock cycle of the second set of multiple clock cycles; and
applying a second delay offset to a rising transition and a falling transition of a second clock cycle of the second set of multiple clock cycles, the second delay offset being different from the first delay offset;
monitoring for a difference in a phase of the output clock signal and a phase of the input clock signal to ensure that respective periods of the output clock signal are not less than a period of the input clock signal;
in response to detecting a difference in the phase of the output clock signal and the phase of the input clock signal, generating a feedback signal based on the difference in the phase of the output clock signal and the phase of the input clock signal; and
adjusting the delaying of the rising transitions and the falling transitions of each of the second set of multiple clock cycles to prevent the period of the third set of multiple clock cycles in the output clock signal from being less than the period of the first set of multiple clock cycles in the input clock signal.