US 12,353,106 B2
Liquid crystal display device
Jang-Kun Song, Seoul (KR); Yeon-Sik Ham, Suwon-si (KR); Kang-Woo Kim, Seoul (KR); Yeon-Mun Jeon, Iksan-si (KR); and Jeong Hyun Lee, Asan-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., Ltd., Yongin (KR)
Filed on Sep. 14, 2023, as Appl. No. 18/466,906.
Application 18/466,906 is a continuation of application No. 17/503,645, filed on Oct. 18, 2021, granted, now 11,803,090.
Application 17/503,645 is a continuation of application No. 16/434,430, filed on Jun. 7, 2019, granted, now 11,150,529, issued on Oct. 19, 2021.
Application 16/434,430 is a continuation of application No. 15/604,721, filed on May 25, 2017, granted, now 10,488,726, issued on Nov. 26, 2019.
Application 15/604,721 is a continuation of application No. 14/322,567, filed on Jul. 2, 2014, granted, now 9,664,968, issued on May 30, 2017.
Application 14/322,567 is a continuation of application No. 12/899,019, filed on Oct. 6, 2010, granted, now 8,804,081, issued on Aug. 12, 2014.
Claims priority of application No. 10-2009-0127314 (KR), filed on Dec. 18, 2009; application No. 10-2009-0127315 (KR), filed on Dec. 18, 2009; and application No. 10-2009-0127316 (KR), filed on Dec. 18, 2009.
Prior Publication US 2024/0004250 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/136 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/155 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/1343 (2013.01); G02F 1/134336 (2013.01); G02F 1/136227 (2013.01); G02F 1/134345 (2021.01); G02F 1/134363 (2013.01); G02F 1/134381 (2021.01); G02F 1/155 (2013.01); G02F 2001/1552 (2013.01); G02F 2201/50 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display device comprising:
a first substrate;
a gate line disposed on the first substrate and extending substantially in a first direction;
a gate electrode protruding from the gate line in a second direction crossing the first direction;
a common voltage line separated from the gate line;
a data line crossing the gate line and including a source electrode, the data line having two opposing edges each extending substantially in the second direction;
a thin film transistor including the gate electrode, the source electrode, a drain electrode opposing the source electrode, and a channel area between the source electrode and the drain electrode;
a pixel electrode connected to the drain electrode of the thin film transistor;
a common electrode disposed on the first substrate and overlapping the pixel electrode; and
an insulating layer between the common voltage line and the common electrode, the insulating layer defining a contact hole,
wherein
the common electrode is electrically connected to the common voltage line through the contact hole, and
the common electrode defines:
a plurality of slits overlapping the pixel electrode,
an enclosed opening overlapping the gate electrode, a portion of the gate line which is adjacent to the gate electrode, an entire width of the source electrode along the first direction, the channel area, and the two opposing edges of the data line in a plan view, and
an outer boundary of the enclosed opening of the common electrode having a first edge crossing the data line, and a second edge crossing the data line,
wherein
the outer boundary of the enclosed opening surrounds the gate electrode, and
the first edge and the second edge oppose each other in the second direction in the plan view with an entirety of the gate electrode and entire width of the gate line along the second direction between the first edge and the second edge.