US 12,353,012 B1
Method for manufacturing an optical switching system
Yakov Roizin, Afula (IL); and Avi Strum, Haifa (IL)
Assigned to Tower Semiconductor Ltd., Migdal Haemek (IL)
Filed by Tower Semiconductor Ltd., Migdal Haemek (IL)
Filed on Aug. 30, 2024, as Appl. No. 18/822,024.
Application 18/822,024 is a continuation of application No. 18/822,015, filed on Aug. 30, 2024.
Int. Cl. G02B 6/35 (2006.01); G02B 6/136 (2006.01); G02B 6/12 (2006.01)
CPC G02B 6/136 (2013.01) [G02B 6/3502 (2013.01); G02B 6/3546 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12145 (2013.01); G02B 2006/12176 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing an optical system, the method comprises:
obtaining an intermediate semiconductor item that comprises a silicon substrate and a stack of layers that comprises a monocrystalline silicon layer and is positioned between two silicon alloy layers; wherein the silicon substrate comprises diffusion regions; and
performing Complementary Metal-Oxide-Semiconductor (CMOS) compliant operations to provide, based on the intermediate semiconductor item, a first switching cell that is formed on the silicon substrate,
wherein the first switching cell comprises: a first port, a second port, a third port, a monocrystalline silicon waveguide (MSW) that comprises a first MSW segment and a second MSW segment, and an actuation unit that is configured to move each one of the first MSW segment and the second MSW segment between at least three different positions thereby determining whether an optical signal received at the first port is (a) directed through the MSW to the second port, or (b) is directed to the third port through a first bus waveguide; wherein the performing of the CMOS compliant operations processes comprises etching the stack of layers by an etching process that exhibits a higher etching rate of the silicon alloy layers in comparison to an etching rate of the monocrystalline silicon layer.