US 12,353,007 B2
Optical wafer-scale photodiode bandwidth measurement system
Attila Mekis, Carlsbad, CA (US); and Gianlorenzo Masini, Carlsbad, CA (US)
Assigned to Cisco Technology, Inc., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Jan. 18, 2023, as Appl. No. 18/156,280.
Prior Publication US 2024/0241309 A1, Jul. 18, 2024
Int. Cl. G02B 6/12 (2006.01); G01R 31/317 (2006.01); G02B 6/42 (2006.01); G02F 1/225 (2006.01)
CPC G02B 6/12019 (2013.01) [G01R 31/31728 (2013.01); G02B 6/4266 (2013.01); G02F 1/2257 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A photonic chip, comprising:
a first optical interface for receiving a first optical signal;
a first photodiode (PD) configured to generate a DC bias using the first optical signal;
a second PD that is biased by the DC bias generated by the first photodiode;
a second optical interface configured to receive a tunable optical signal for testing a bandwidth of the second PD, wherein the second PD generates a varying AC signal based on the tunable optical signal;
a resistor, wherein the varying AC signal heats the resistor;
an interferometer thermally coupled to the resistor;
a third optical interface for receiving a third optical signal that passes through the interferometer; and
a fourth optical interface coupled to an output of the interferometer, wherein an optical output of the interferometer changes in response to heat generated by the resistor.