US 12,352,830 B2
Sensor unit
Kunihiro Ueda, Tokyo (JP); Yoshimitsu Wada, Tokyo (JP); Hiraku Hirabayashi, Tokyo (JP); Kazuma Yamawaki, Tokyo (JP); and Tsuyoshi Umehara, Tokyo (JP)
Assigned to TDK CORPORATION, Tokyo (JP)
Filed by TDK CORPORATION, Tokyo (JP)
Filed on Mar. 18, 2024, as Appl. No. 18/607,811.
Application 18/607,811 is a continuation of application No. 18/180,369, filed on Mar. 8, 2023, granted, now 11,959,979.
Application 18/180,369 is a continuation of application No. 17/703,495, filed on Mar. 24, 2022, granted, now 11,630,165, issued on Apr. 18, 2023.
Application 17/703,495 is a continuation of application No. 16/816,685, filed on Mar. 12, 2020, granted, now 11,313,920, issued on Apr. 26, 2022.
Application 16/816,685 is a continuation of application No. 15/641,529, filed on Jul. 5, 2017, granted, now 10,634,734, issued on Apr. 28, 2020.
Claims priority of application No. 2016-140085 (JP), filed on Jul. 5, 2016; application No. 2016-241461 (JP), filed on Dec. 13, 2016; and application No. 2017-000854 (JP), filed on Jan. 6, 2017.
Prior Publication US 2024/0219484 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 33/00 (2006.01); B82Y 10/00 (2011.01); B82Y 25/00 (2011.01); B82Y 40/00 (2011.01); G01R 15/20 (2006.01); G01R 33/07 (2006.01); G01R 33/09 (2006.01)
CPC G01R 33/0005 (2013.01) [B82Y 10/00 (2013.01); B82Y 25/00 (2013.01); B82Y 40/00 (2013.01); G01R 33/0094 (2013.01); G01R 33/09 (2013.01); G01R 33/091 (2013.01); G01R 33/093 (2013.01); G01R 33/096 (2013.01); G01R 33/098 (2013.01); G01R 15/205 (2013.01); G01R 33/0082 (2013.01); G01R 33/07 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A sensor unit comprising:
a substrate having a substantially-rectangular shape including a pair of first sides and a pair of second sides that are substantially orthogonal to each other;
a circuit chip stacked on the substrate;
a plurality of sensors provided on the circuit chip and arranged on an axis, the axis being substantially parallel to the second side and passing through a center position of the circuit chip; and
a plurality of pads provided on the substrate and arranged along each of pair of first sides.