US 12,352,829 B2
Chip port state detection circuit, chip, and communication terminal
Yongshou Wang, Shanghai (CN); Chenyang Gao, Shanghai (CN); and Sheng Lin, Shanghai (CN)
Assigned to SHANGHAI VANCHIP TECHNOLOGIES CO., LTD., Shanghai (CN)
Filed by SHANGHAI VANCHIP TECHNOLOGIES CO., LTD., Shanghai (CN)
Filed on May 16, 2023, as Appl. No. 18/318,040.
Application 18/318,040 is a continuation of application No. PCT/CN2021/130951, filed on Nov. 16, 2021.
Claims priority of application No. 202011276886.4 (CN), filed on Nov. 16, 2020.
Prior Publication US 2023/0288500 A1, Sep. 14, 2023
Int. Cl. G01R 31/68 (2020.01); G01R 19/155 (2006.01); G01R 19/257 (2006.01)
CPC G01R 31/68 (2020.01) [G01R 19/155 (2013.01); G01R 19/257 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A chip port state detection circuit, comprising a port detection conversion circuit, a reference voltage generation circuit, a first comparator, a second comparator, a dynamic bias current generation circuit, and a chip identifier (ID) determination circuit, wherein the port detection conversion circuit, the reference voltage generation circuit, and the dynamic bias current generation circuit are separately connected to the first comparator and the second comparator; the first comparator and the second comparator are separately connected to the chip ID determination circuit;
the port detection conversion circuit is connected to a port to be detected of a chip to convert a state of the port to be detected into a corresponding voltage and separately output the voltage to the first comparator and the second comparator; the first comparator and the second comparator receive input reference voltages provided by the reference voltage generation circuit, compare the voltage output by the port detection conversion circuit with the input reference voltages, and then output logic signals to the chip ID determination circuit; and the chip ID determination circuit outputs a chip ID corresponding to the state of the port to be detected according to the logic signals, so as to distinguish a plurality of identical chips.