US 12,352,826 B2
Current measurement architecture
Ashwani Kumar Srivastava, Austin, TX (US); Yves Thomas Laplanche, Valbonne (FR); and Ramesh Manohar, Bangalore (IN)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Mar. 29, 2023, as Appl. No. 18/127,871.
Prior Publication US 2024/0329153 A1, Oct. 3, 2024
Int. Cl. G01R 31/52 (2020.01)
CPC G01R 31/52 (2020.01) 20 Claims
OG exemplary drawing
 
1. A device comprising:
fabrication test circuitry with transistors arranged in a parallel branch configuration between a supply voltage and a single pad,
wherein each transistor in an off-current branch is separately deactivated so as to test leakage current applied to the single pad by way of the off-current branch, and
wherein each transistor in an on-current branch is deactivated so as to further test the leakage current applied to the single pad by way of the off-current branch.