US 12,352,813 B2
Integrated circuit and an electronic device including integrated circuit
Yeon Ho Jung, Suwon-si (KR); Jong Wook Kye, Suwon-si (KR); Min Woo Kwak, Seoul (KR); Mi Joung Kim, Hwaseong-si (KR); Chan Wook Park, Seongnam-si (KR); Do Hoon Byun, Hwaseong-si (KR); Je Kyun Ryu, Seoul (KR); Kwan Seong Lee, Yongin-si (KR); Jae Ho Lee, Incheon (KR); and Jae Seung Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 6, 2022, as Appl. No. 17/662,327.
Claims priority of application No. 10-2021-0127124 (KR), filed on Sep. 27, 2021.
Prior Publication US 2023/0097976 A1, Mar. 30, 2023
Int. Cl. G01R 31/317 (2006.01); H03K 17/693 (2006.01)
CPC G01R 31/31712 (2013.01) [G01R 31/31724 (2013.01); H03K 17/693 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a sequential logic circuit, which includes a first scan cell that is configured to receive a scan input, and a plurality of scan cells sequentially connected in series from the first scan cell;
a control unit, which is configured to receive a selection signal comprising an output of each of the plurality of scan cells, and is further configured to output a control signal responsive to the selection signal;
a monitoring circuit, which is configured to receive the control signal, is configured to perform first monitoring of first data at a first node that is an observation node in the sequential logic circuit responsive to the control signal, and is configured to output a result of the first monitoring to a monitoring node;
an input multiplexer, which is configured to receive the first data and data corresponding to the first monitoring, and is configured to output one of the first data or the data corresponding to the first monitoring responsive to a verification signal that is received; and
an inverter that is coupled between the monitoring node and the input multiplexer and is configured to invert the result of the first monitoring.