US 12,352,811 B1
Validating test patterns ported between different levels of a hierarchical design of an integrated circuit
Andrea Costa, Delta (CA); Frederic Jean Neuveux, Grenoble (FR); Salvatore Talluto, Gavirate (IT); Sorin Ioan Popa, Saint-Ismier (FR); and Leela Krishna Thota, Bangalore (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 30, 2023, as Appl. No. 18/345,962.
Int. Cl. G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3181 (2006.01)
CPC G01R 31/2884 (2013.01) [G01R 31/31704 (2013.01); G01R 31/31813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a block-level design for a block of circuitry, the block containing at least one sub-block;
receiving sub-level test patterns for the sub-block, wherein the sub-level test patterns comprise (a) sub-level test stimuli applied to inputs of the sub-block (sub-block inputs), and (b) sub-level test responses expected at outputs of the sub-block (sub-block outputs) in response to the sub-level test stimuli;
receiving block-level test patterns that include (x) block-level test stimuli comprising the sub-level test stimuli ported to inputs of the block of circuitry (block inputs), and (y) block-level test responses comprising the sub-level test responses ported to outputs of the block of circuitry (block outputs); and
validating, by a processing device, the block-level test patterns, comprising:
computing propagation of the block-level test stimuli through the block-level design;
comparing signals produced by such computed propagation at the sub-block inputs against the sub-level test stimuli; and
comparing signals produced by such computed propagation at the block outputs against the block-level test responses.