US 12,352,794 B2
Capacitance measurement circuit
Yanhan Zeng, Guangzhou (CN); Haochang Zhi, Guangzhou (CN); Yongnan Chen, Guangzhou (CN); Junkai Chen, Guangzhou (CN); Jingci Yang, Guangzhou (CN); and Tianxian Wu, Guangzhou (CN)
Assigned to Guangzhou University, Guangzhou (CN)
Filed by Guangzhou University, Guangzhou (CN)
Filed on Apr. 12, 2023, as Appl. No. 18/299,088.
Application 18/299,088 is a continuation of application No. PCT/CN2021/111758, filed on Aug. 10, 2021.
Claims priority of application No. 202010806476.X (CN), filed on Aug. 12, 2020.
Prior Publication US 2023/0314495 A1, Oct. 5, 2023
Int. Cl. G01R 27/26 (2006.01)
CPC G01R 27/2605 (2013.01) 7 Claims
OG exemplary drawing
 
1. A capacitance measurement circuit, comprising: an analog front-end circuit, a parasitic capacitor, an analog to digital converter (ADC), an output shift register, and a controller;
wherein input terminals of the ADC are connected to an output terminal of the analog front-end circuit, and an output terminal of the ADC is connected to the output shift register;
wherein an input terminal of the analog front-end circuit is connected to the parasitic capacitor and a capacitor to be measured individually; the analog front-end circuit comprises M numbers of current mirror circuits connected in parallel, where M=2N−1 and N is a positive integer;
wherein the controller is configured to control the analog front-end circuit, the parasitic capacitor, the ADC, and the output shift register to measure the capacitor to be measured, specifically to:
step 1, control one of the current mirror circuits of the analog front-end circuit to be turned on;
step 2, disconnect the capacitor to be measured, and control an inverting input terminal of the ADC to continuously collect analog front end (AFE) output voltages of the analog front-end circuit before connection of the capacitor to be measured;
step 3, control the analog front-end circuit to charge the parasitic capacitor to a first reference voltage, and record an AFE output voltage VN currently collected at the inverting input terminal of the ADC;
step 4, connect the capacitor to be measured, after the analog front-end circuit is stabilized, control a non-inverting input terminal of the ADC to collect an AFE output voltage VP of the analog front-end circuit, and control the ADC to convert a difference value (VP−VN) of the AFE output voltage VP and the AFE output voltage VN into a first digital signal;
step 5, determine, based on a value of the first digital signal, a connection number m of the current mirror circuits, and control the m numbers of current mirror circuits of the analog front-end circuit to be turned on; where m=2n−1 and n is a positive integer less than or equal to N; and
step 6, repeat the step 2 to step 4 to obtain a second digital signal, and control, based on the connection number m, the output shift register to shift the second digital signal to obtain a capacitance measurement value of the capacitor to be measured.