US RE48,625 E1
Memory circuit having non-volatile memory cell and methods of using
Ronald L Cline, San Jose, CA (US); and Stewart G. Logie, Campbell, CA (US)
Assigned to Lattice Semiconductor Corporation, Portland, OR (US)
Filed by Lattice Semiconductor Corporation, Portland, OR (US)
Filed on May 9, 2018, as Appl. No. 15/975,506.
Application 15/975,506 is a reissue of application No. 14/887,174, filed on Oct. 19, 2015, granted, now 9,672,935, issued on Jun. 6, 2017.
Claims priority of provisional application 62/065,241, filed on Oct. 17, 2014.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/16 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01); G11C 16/10 (2006.01)
CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01); G11C 16/10 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An article of manufacture comprising a memory circuit comprising:
volatile output circuitry (VOC); and
a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:
a first anti-fuse device [ non-volatile memory element] ;
a second anti-fuse device [ non-volatile memory element] ;
a first select device connected in series with the first anti-fuse device [ non-volatile memory element ] at a first node [ , wherein the first select device has a first terminal and a second terminal] ;
a second select device connected in series with the second anti-fuse device [ non-volatile memory element ] at a second node [ , wherein the second select device has a first terminal and a second terminal, wherein the first select device's first terminal is connected to the second select device's first terminal, and wherein the first select device's second terminal is connected to the second select device's second terminal] ;
a first pass device connected between the first node and a VOC input node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the VOC input node; and
a second pass device connected between the second node and the VOC input node and usable to selectively pass a voltage at the second node to the VOC input node, wherein the volatile output circuitry is connected to receive the NVM output signal from the NVM cell at the VOC input node and generate a VOC output signal indicative of the program state of the NVM cell.