US 11,057,975 B2
Two-terminal integrated circuits with time varying voltage-current characteristics including phased-locked power supplies
Qiang Luo, Shanghai (CN); Liqiang Zhu, Shanghai (CN); Zhiliang Chen, Shanghai (CN); and Lieyi Fang, Shanghai (CN)
Assigned to On-Bright Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed by ON-BRIGHT ELECTRONICS (SHANGHAI) CO., LTD., Shanghai (CN)
Filed on Apr. 17, 2020, as Appl. No. 16/851,249.
Application 16/851,249 is a continuation of application No. 15/836,588, filed on Dec. 8, 2017, granted, now 10,681,786.
Application 15/836,588 is a continuation of application No. 15/184,821, filed on Jun. 16, 2016, granted, now 9,883,557, issued on Jan. 30, 2018.
Claims priority of application No. 201610345806.3 (CN), filed on May 23, 2016.
Prior Publication US 2020/0323062 A1, Oct. 8, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H05B 45/37 (2020.01); H05B 45/48 (2020.01); H05B 45/395 (2020.01)
CPC H05B 45/37 (2020.01) [H05B 45/395 (2020.01); H05B 45/48 (2020.01)] 26 Claims
OG exemplary drawing
 
1. A two-terminal IC chip, the chip comprising:
a first chip terminal; and
a second chip terminal;
wherein:
a first terminal voltage is a voltage of the first chip terminal;
a second terminal voltage is a voltage of the second chip terminal; and
a chip voltage is equal to a difference between the first terminal voltage and the second terminal voltage;
wherein the chip is configured to:
allow a chip current to flow into the chip at the first chip terminal and out of the chip at the second chip terminal, or to flow into the chip at the second chip terminal and out of the chip at the first chip terminal, the chip current being larger than or equal to zero in magnitude;
allow the chip current flowing into the chip at the first chip terminal to power one or more internal power supplies; and
change a relationship between the chip voltage and the chip current with respect to time;
wherein:
the chip is an integrated circuit; and
the chip does not include any additional chip terminal other than the first chip terminal and the second chip terminal.