US 11,057,194 B2
Processing system, related integrated circuit, device and method
Roberto Colombo, Munich (DE); Guido Marco Bertoni, Bernareggio (IT); William Orlando, Peynier (FR); and Roberta Vittimani, Agrate Brianza (IT)
Filed by STMicroelectronics Application GMBH, Ascheim-Dornach (DE); and STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jun. 28, 2018, as Appl. No. 16/22,033.
Claims priority of application No. 102017000074269 (IT), filed on Jul. 3, 2017; and application No. 102017000074295 (IT), filed on Jul. 3, 2017.
Prior Publication US 2019/0007201 A1, Jan. 3, 2019
Int. Cl. H04L 9/08 (2006.01); G06F 13/36 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01)
CPC H04L 9/0819 (2013.01) [G06F 13/36 (2013.01); H04L 9/0897 (2013.01); H04L 9/14 (2013.01); H04L 9/3239 (2013.01); H04L 2209/38 (2013.01)] 22 Claims
OG exemplary drawing
1. A processing system, comprising:
a first processing unit driven with a first clock signal;
a second processing unit driven with a second clock signal, wherein a frequency of the second clock signal is less than a frequency of the first clock signal;
a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit, wherein the first processing unit, the second processing unit and the cryptographic coprocessor are in close proximity within the processing system;
a transmission system coupled between the first processing unit and the second processing unit, the transmission system providing a transmission path between the first and second processing units outside the cryptographic coprocessor;
the cryptographic coprocessor comprising:
a key storage memory for storing a cryptographic key;
a first interface configured to receive source data to be processed directly from the first processing unit;
a hardware cryptographic engine driven with the first clock signal that is configured to process the source data as a function of the cryptographic key stored in the key storage memory;
a second interface configured to receive a first cryptographic key directly from the second processing unit; and
a hardware key management circuit driven with the second clock signal that is configured to store the first cryptographic key in the key storage memory.