US 11,057,070 B1
Signal receiving device adapting to signal input mode and signal processing method for the same
Chen-Kang Lin, Hsinchu County (TW); Hung-Yi Chang, Hsinchu (TW); and Bing-Juo Chuang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Oct. 14, 2020, as Appl. No. 17/69,961.
Claims priority of application No. 109100529 (TW), filed on Jan. 8, 2020.
Int. Cl. H04B 1/18 (2006.01); H04L 25/02 (2006.01); H04L 7/00 (2006.01); H04B 1/40 (2015.01)
CPC H04B 1/18 (2013.01) [H04B 1/40 (2013.01); H04L 7/0008 (2013.01); H04L 25/0272 (2013.01); H04L 25/0296 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A signal receiving device adapting to a signal input mode, comprising:
a first multiplexer having a first input terminal and a second input terminal respectively receiving a first input signal and a second input signal, and an output terminal outputting a first output signal, wherein the first multiplexer selects the first input signal to be output as the first output signal in an initial state;
a second multiplexer having a first input terminal and a second input terminal respectively receiving the first input signal and the second input signal, and an output terminal outputting a second output signal, wherein the second multiplexer selects the second input signal to be output as the second output signal in the initial state;
a third multiplexer having a first input terminal receiving a DC signal DC-converted from the first output signal, a second input terminal receiving the second output signal, and an output terminal outputting a third output signal, wherein the third multiplexer selects the second output signal to be output as the third output signal in the initial state; and
a control circuit having a first input terminal and a second input terminal respectively receiving the first output signal and the third output signal, wherein the control circuit is configured to mutually subtract the first output signal and the third output signal to generate a first difference signal and a second difference signal, respectively count numbers of signal edges of the first difference signal and the second difference signal within a first preset time, and determine whether the signal input mode is a differential signal according to the numbers of the signal edges counted within the first preset time, wherein in response to the signal input mode being determined not to be the differential signal, the control circuit outputs a mode selecting signal with a first logic level to control the third multiplexer to select the DC signal to be output as the third output signal, and wherein in response to the signal input mode being determined as the differential signal, the control circuit outputs the mode selecting signal with a second logic level to control the third multiplexer to keep selecting the second output signal to be output as the third output signal.