US 11,057,028 B2
Double clock architecture for small duty cycle DC-DC converter
Alessandro Bertolini, Vermiglio (IT); Alberto Cattani, Cislago (IT); Stefano Ramorini, Arluno (IT); and Alessandro Gasparini, Cusano Milanino (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Sep. 3, 2019, as Appl. No. 16/559,118.
Prior Publication US 2021/0067148 A1, Mar. 4, 2021
Int. Cl. H03K 3/017 (2006.01); H03K 5/04 (2006.01); H03K 7/08 (2006.01); H03K 5/156 (2006.01); H02M 3/158 (2006.01)
CPC H03K 5/1565 (2013.01) [H02M 3/1582 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A DC-DC converter boosting an input voltage to an output voltage, the DC-DC converter comprising:
clock generation circuitry configured to generate first and second clock signals that are out of phase with each other;
a control signal generator configured to generate a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage;
boost circuitry configured to charge an energy storage component during an on-phase and to discharge the energy storage component during an off-phase to thereby generate the output voltage, wherein the on-phase and off-phase are set as a function of the switching control signal; and
sum voltage circuitry configured to:
generate a ramp voltage based upon the first clock signal; and
from a falling edge of the second clock signal until an end of the on-phase, generate the summed voltage to represent a sum of the ramp voltage and a voltage representative of a current signal carrying information about a storage component current flowing in the energy storage component during the on-phase, but from a beginning of the off-phase until a next falling edge of the second clock signal, generate the summed voltage to represent only the ramp voltage, the off-phase beginning at the end of the on-phase.