US 11,057,027 B2
Circuit having a plurality of modes
Szu-Yang Chang, Hsinchu (TW)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Jul. 21, 2020, as Appl. No. 16/935,158.
Claims priority of application No. 108129943 (TW), filed on Aug. 22, 2019.
Prior Publication US 2021/0058079 A1, Feb. 25, 2021
Int. Cl. H03K 5/15 (2006.01); H03K 5/135 (2006.01); H03L 7/07 (2006.01); H03K 5/156 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/15066 (2013.01) [H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03L 7/07 (2013.01); H03K 2005/00013 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A circuit having a plurality of modes, comprising:
a first circuit, arranged to generate a first signal;
a second circuit, arranged to generate a second signal;
a first multiplexer, coupled to the first circuit and the second circuit, arranged to output one of the first signal and the second signal according to a mode selection signal;
a second multiplexer, arranged to output one of a first clock signal and a second clock signal according to the mode selection signal;
a specific flip-flop, coupled to the first multiplexer and the second multiplexer, arranged to sample the first signal or the second signal outputted by the first multiplexer by using the first clock signal or the second clock signal outputted by the second multiplexer to generate an output signal of the specific flip-flop; and
a delay circuit, arranged to delay the second clock signal to generate the first clock signal;
wherein the first circuit comprises:
a first flip-flop, arranged to generate an output signal of the first flip-flop according to the second clock signal; and
a logical circuit, arranged to generate the first signal according to the output signal of the first flip-flop; and
the second circuit comprises:
a second flip-flip, arranged to generate the second signal according to the second clock signal.