US 11,057,025 B2
Level shifter
Chien-Yuan Chen, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); Hung-Jen Liao, Hsinchu (TW); and Hau-Tai Shieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 11, 2020, as Appl. No. 17/17,993.
Application 17/017,993 is a continuation of application No. 16/842,910, filed on Apr. 8, 2020, granted, now 10,778,198.
Application 16/842,910 is a continuation of application No. 16/389,461, filed on Apr. 19, 2019, granted, now 10,651,832, issued on May 12, 2020.
Claims priority of provisional application 62/717,206, filed on Aug. 10, 2018.
Prior Publication US 2020/0412346 A1, Dec. 31, 2020
Int. Cl. H03K 3/356 (2006.01); H03K 19/0185 (2006.01); H03K 17/687 (2006.01); G11C 11/56 (2006.01)
CPC H03K 3/356156 (2013.01) [G11C 11/5621 (2013.01); H03K 17/6871 (2013.01); H03K 19/018521 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A level shifter comprising:
a first inverter configured to receive an input signal in a first voltage domain and shift the input signal from the first voltage domain to a first output signal at a first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of a first clock signal in the first voltage domain;
a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the first voltage domain to a second output signal at a second output terminal in the second voltage domain in response to the logical high state of the first clock signal;
a pair of NMOS sensing transistors including a first NMOS sensing transistor and a second NMOS sensing transistor having a common source terminal, wherein a drain terminal of the first NMOS sensing transistor is coupled to the first inverter, a gate terminal of the first NMOS sensing transistor is configured to receive the input signal, a drain terminal of the second NMOS sensing transistor is coupled to the second inverter, and a gate terminal of the second NMOS sensing transistor is configured to receive the complement of the input signal; and
a PMOS transistor coupled between the first output terminal and the second output terminal and having a gate terminal connected to receive the first clock signal in the first voltage domain, the PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal.