US 11,056,879 B2
Snapback clamps for ESD protection with voltage limited, centralized triggering scheme
Michael A. Stockinger, Austin, TX (US); Marcin Grad, Bemmel (NL); Paul Hendrik Cappon, Wijchen (NL); and Sjoerd Bruinsma, Malden (NL)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jun. 12, 2019, as Appl. No. 16/438,682.
Prior Publication US 2020/0395751 A1, Dec. 17, 2020
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01)
CPC H02H 9/046 (2013.01) [H01L 27/0277 (2013.01); H01L 27/0629 (2013.01)] 20 Claims
OG exemplary drawing
1. An integrated circuit (IC) comprising:
a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event;
a plurality of metal oxide semiconductor (MOS) transistors coupled to the trigger circuit, wherein the plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a first conductor in response to the trigger circuit generating the trigger voltage VT;
a voltage limiter circuit configured to limit the trigger voltage VT.