US 11,056,569 B2
Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
Daniel E. Grupp, Palo Alto, CA (US); and Daniel J. Connelly, Redwood City, CA (US)
Assigned to Acorn Semi, LLC, Palo Alto, CA (US)
Filed by Acorn Semi, LLC, Palo Alto, CA (US)
Filed on Jul. 9, 2019, as Appl. No. 16/506,022.
Application 13/022,522 is a division of application No. 12/197,996, filed on Aug. 25, 2008, granted, now 7,884,003, issued on Feb. 8, 2011.
Application 12/197,996 is a division of application No. 11/181,217, filed on Jul. 13, 2005, granted, now 7,462,860, issued on Dec. 9, 2008.
Application 16/506,022 is a continuation of application No. 15/728,002, filed on Oct. 9, 2017, granted, now 10,388,748.
Application 15/728,002 is a continuation of application No. 15/251,210, filed on Aug. 30, 2016, granted, now 9,812,542, issued on Nov. 7, 2017.
Application 15/251,210 is a continuation of application No. 15/048,877, filed on Feb. 19, 2016, granted, now 9,905,691, issued on Feb. 27, 2018.
Application 15/048,877 is a continuation of application No. 13/552,556, filed on Jul. 18, 2012, granted, now 9,425,277, issued on Aug. 23, 2016.
Application 13/552,556 is a continuation of application No. 13/022,522, filed on Feb. 7, 2011, granted, now 8,431,469, issued on Apr. 30, 2013.
Application 11/181,217 is a continuation of application No. 10/217,758, filed on Aug. 12, 2002, granted, now 7,084,423, issued on Aug. 1, 2006.
Prior Publication US 2019/0334006 A1, Oct. 31, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/45 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/80 (2006.01); H01L 29/812 (2006.01); H01L 29/872 (2006.01); H01L 21/285 (2006.01)
CPC H01L 29/456 (2013.01) [H01L 21/28537 (2013.01); H01L 29/0895 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01); H01L 29/66143 (2013.01); H01L 29/66643 (2013.01); H01L 29/78 (2013.01); H01L 29/7839 (2013.01); H01L 29/806 (2013.01); H01L 29/812 (2013.01); H01L 29/872 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electrical junction, comprising:
a semiconductor region in a substrate;
a metal electrical contact proximate to said semiconductor region; and
an interface layer disposed between said semiconductor region and said metal electrical contact, said interface layer including a first layer containing a passivating material and a second layer that displaces the semiconductor region from the metal electrical contact, said semiconductor region being electrically connected to said metal electrical contact through said interface layer.