US 11,056,556 B2
Metal-insulator-metal capacitive structure and methods of fabricating thereof
Hsiang-Ku Shen, Hsinchu (TW); Ming-Hong Kao, Hsinchu (TW); Hui-Chi Chen, Hsinchu County (TW); Dian-Hau Chen, Hsinchu (TW); and Yen-Ming Chen, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 12, 2019, as Appl. No. 16/439,385.
Claims priority of provisional application 62/738,478, filed on Sep. 28, 2018.
Prior Publication US 2020/0105863 A1, Apr. 2, 2020
Int. Cl. H01L 49/02 (2006.01)
CPC H01L 28/60 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a top metal layer and an inter-metal dielectric (IMD);
forming a first silicon oxide layer adjacent a bottom electrode, wherein the forming the first silicon oxide layer includes: forming an opening in a conductive material to provide the bottom electrode, wherein the forming the opening includes etching the conductive material and a portion of the IMD, and chemical vapor deposition of silicon oxide into the opening;
depositing a first high-k dielectric layer over the bottom electrode and the first silicon oxide layer;
forming a middle electrode over the first high-k dielectric layer;
forming a second silicon oxide layer adjacent the middle electrode;
depositing a second high-k dielectric layer over the middle electrode and the second silicon oxide layer; and
forming a top electrode over the second high-k dielectric layer.