US 11,056,537 B2
Self-aligned gate contact integration with metal resistor
Xin Miao, Slingerlands, NY (US); Richard A. Conti, Altamont, NY (US); Ruilong Xie, Niskayuna, NY (US); and Kangguo Cheng, Schenectady, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 27, 2019, as Appl. No. 16/366,309.
Prior Publication US 2020/0312909 A1, Oct. 1, 2020
Int. Cl. H01L 21/28 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01); H01L 21/768 (2006.01)
CPC H01L 27/2436 (2013.01) [H01L 21/28518 (2013.01); H01L 27/2463 (2013.01); H01L 29/45 (2013.01); H01L 29/66515 (2013.01); H01L 45/1608 (2013.01); H01L 21/76897 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of fabricating a middle-of-line (MOL) structure comprising a device region and a resistive memory (RM) region, the method comprising:
forming lower source/drain (S/D) metallization interleaved with gate elements in the device region; recessing interlayer dielectric (ILD) in the device region and RM region; disposing an RM resistor over the recessed ILD in the RM region; recessing the lower S/D metallization in the device region; forming a dielectric cap over the recessed lower S/D metallization and the recessed ILD in the device region and over the RM resistor in the RM region; forming first S/D contacts to the S/D metallization in the device region; forming second S/D contacts to the gate elements in the device region; and forming an S/D contact to the RM resistor in the RM region.