US 11,056,504 B2
Memory device
Yu-Wei Jiang, Hsinchu (TW); and Jia-Rong Chiou, Zhubei (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Oct. 23, 2019, as Appl. No. 16/661,040.
Prior Publication US 2021/0126006 A1, Apr. 29, 2021
Int. Cl. H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/306 (2006.01)
CPC H01L 27/11582 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 29/41741 (2013.01); H01L 29/4234 (2013.01); H01L 29/456 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first channel element and a second channel element each having an open ring shape, wherein opposing ends of the first channel element have a first convex curved sidewall surface and a second convex curved sidewall surface respectively, opposing ends of the second channel element have a third convex curved sidewall surface and a fourth convex curved sidewall surface respectively, wherein the opposing ends of the first channel element have a source side element and a drain side element respectively, a portion of the first channel element between the source side element and the drain side element has a size smaller than a size of the source side element, the size of the first channel element is smaller than a size of the drain side element;
an insulating layer disposed between the first convex curved sidewall surface of the first channel element and the third convex curved sidewall surface of the second channel element, and disposed between the second convex curved sidewall surface of the first channel element and the fourth convex curved sidewall surface of the second channel element, wherein the first channel element is insulated from the second channel element by the insulating layer;
a first memory element and a second memory element; and
a first electrode element and a second electrode element, wherein a first memory cell is defined in the first memory element between the first channel element and the first electrode element, and a second memory cell is defined in the second memory element between the second channel element and the second electrode element.