US 11,056,498 B2
Semiconductor device and manufacturing method therefor
Jinshuang Zhang, Shanghai (CN); Haoyu Chen, Shanghai (CN); Qiwei Wang, Shanghai (CN); and Feng Ji, Shanghai (CN)
Assigned to SHANGHAI HUALI MICROELECTRONICS CORPORATION, Shanghai (CN)
Filed by Shanghai Huali Microelectronics Corporation, Shanghai (CN)
Filed on Apr. 16, 2019, as Appl. No. 16/384,966.
Claims priority of application No. 201810714188.4 (CN), filed on Jun. 29, 2018.
Prior Publication US 2020/0006372 A1, Jan. 2, 2020
Int. Cl. H01L 27/11573 (2017.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 27/11565 (2017.01)
CPC H01L 27/11573 (2013.01) [H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 21/76837 (2013.01); H01L 27/11565 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A manufacturing method for a semiconductor device, configured for forming through-holes in the semiconductor device, wherein the semiconductor device comprises memory cell regions, the manufacturing method comprising:
providing a substrate;
forming a plurality of shallow trench isolations in portions of the substrate corresponding to the memory cell regions, wherein the shallow trench isolations are arranged spaced apart from each other in a first direction and extend in a second direction to define active regions of the substrate which are spaced apart by the shallow trench isolations, the first direction being perpendicular to the second direction;
forming a plurality of gates on surfaces of the portions of the substrate, wherein the gates extend in the first direction and are arranged spaced apart from each other in the second direction;
forming spacers on side walls at both sides of the gates extending in the first direction;
depositing a sacrificial layer on the memory cell region, wherein the sacrificial layer covers the gates and fills gaps between the gates;
removing portions of the sacrificial layer corresponding to the shallow trench isolations at memory cell drain, and depositing an isolation dielectric on the shallow trench isolations at the memory cell drain to form isolation strips; and
removing the remaining sacrificial layer to form bottom through-holes in spaces formed after removing the remaining sacrificial layer, wherein the bottom through-holes comprise drain bottom through-holes of the active regions corresponding to the memory cell drain and source bottom through-holes corresponding to memory cell source;
wherein a material of the sacrificial layer is different from the materials of the spacers, the isolation dielectric, and the shallow trench isolations.