US 11,056,493 B2
Semiconductor structures with deep trench capacitor and methods of manufacture
Kevin K. Chan, Staten Island, NY (US); Sivananda K. Kanakasabapathy, Pleasanton, CA (US); Babar A. Khan, Ossining, NY (US); Masaharu Kobayashi, Tokyo (JP); Effendi Leobandung, Stormville, NY (US); Theodorus E. Standaert, Clifton Park, NY (US); and Xinhui Wang, Poughkeepsie, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 7, 2019, as Appl. No. 16/295,505.
Application 14/511,413 is a division of application No. 13/804,647, filed on Mar. 14, 2013, granted, now 8,987,800, issued on Mar. 24, 2015.
Application 16/295,505 is a continuation of application No. 15/940,009, filed on Mar. 29, 2018, granted, now 10,269,806.
Application 15/940,009 is a continuation of application No. 15/285,520, filed on Oct. 5, 2016, granted, now 10,042,968, issued on Aug. 7, 2018.
Application 15/285,520 is a continuation of application No. 14/511,413, filed on Oct. 10, 2014, granted, now 9,576,096, issued on Feb. 21, 2017.
Prior Publication US 2019/0206871 A1, Jul. 4, 2019
Int. Cl. H01L 27/108 (2006.01); H01L 27/07 (2006.01); H01L 27/12 (2006.01); H01L 29/94 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/10 (2020.01); H01L 49/02 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 27/06 (2006.01)
CPC H01L 27/10832 (2013.01) [G06F 30/10 (2020.01); G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/0733 (2013.01); H01L 27/10826 (2013.01); H01L 27/10829 (2013.01); H01L 27/10858 (2013.01); H01L 27/10867 (2013.01); H01L 27/10879 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 28/40 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/517 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01); H01L 27/0629 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A structure, comprising:
a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure including epitaxial material comprising semiconductor material over exposed sidewalls of fin structures and semiconductor material of SOI fins each of which have ends in contact with respective fin structures of the deep trench capacitors, a gate structure extending directly on a top surface of the SOI fins, and sidewalls on the gate structure comprise insulator material,
wherein the fin structure of the deep trench capacitors extends above a top surface of the SOI substrate,
a portion of the deep trench capacitors below the fin structure includes a dielectric material lining a trench, a metal layer on the dielectric material, and remaining portions of the trench filled with polysilicon material, in contact with the epitaxial material of the fin structure of the deep trench capacitors,
the gate structure comprises a gate dielectric material directly on a buried oxide layer, a second semiconductor material directly on the gate dielectric material, a capping material directly on the second semiconductor material, sidewall materials directly on the capping material, the second semiconductor material, and the gate dielectric material of the gate structure, and the fin structures are polysilicon formed in direct contact with the SOI fins using the epitaxial material to provide a connection between the SOI fins and a top surface and side surfaces of the fin structures, and the polysilicon material is between the metal layer and the dielectric material in the deep trench capacitors.