US 11,056,486 B2
Semiconductor device with multiple threshold voltage and method of fabricating the same
Li-Ting Wang, Hsinchu (TW); Teng-Chun Tsai, Hsinchu (TW); Cheng-Tung Lin, Jhudong Township (TW); De-Fang Chen, Hsinchu (TW); and Hui-Cheng Chang, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Mar. 28, 2019, as Appl. No. 16/368,827.
Application 16/368,827 is a continuation of application No. 14/148,825, filed on Jan. 7, 2014, granted, now 10,276,562.
Prior Publication US 2019/0229118 A1, Jul. 25, 2019
Int. Cl. H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/26586 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 29/42392 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vertical semiconductor field effect transistor (FET), comprising:
a source;
a channel over the source;
a drain over the channel;
a gate dielectric layer adjacent to a lateral surface of the channel;
a first conductive layer adjacent to the gate dielectric layer; and
a gate metal layer adjacent to the first conductive layer,
wherein the first conductive layer includes TiN or TaN, which further comprises Te.