US 11,056,478 B2
Metal gate structure cutting process
Shiang-Bau Wang, Pingzchen (TW); Ryan Chia-Jen Chen, Chiayi (TW); Shu-Yuan Ku, Zhubei (TW); and Ming-Ching Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 29, 2018, as Appl. No. 16/203,755.
Application 16/203,755 is a division of application No. 15/809,898, filed on Nov. 10, 2017, granted, now 10,269,787.
Claims priority of provisional application 62/526,956, filed on Jun. 29, 2017.
Prior Publication US 2019/0109126 A1, Apr. 11, 2019
Int. Cl. H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 29/06 (2006.01); H01L 21/027 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01)
CPC H01L 27/0207 (2013.01) [H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/42372 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 21/0276 (2013.01); H01L 21/28556 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first gate structure and a second gate structure disposed in an interlayer dielectric (ILD) layer disposed on a substrate, wherein each of the first gate structure and the second gate structure comprises a gate dielectric and a gate electrode;
an isolation structure disposed between the first gate structure and the second gate structure, wherein the ILD layer circumscribes a perimeter of the isolation structure; and
a dielectric structure disposed between the ILD layer and the isolation structure, wherein a bottom surface of the isolation structure is closer to the substrate than a bottom surface of the dielectric structure, wherein the isolation structure directly contacts the gate electrode of the first gate structure.